This stage invokes the Xilinx NGDBuild tool, translating the EDIF output from the FPGA project synthesis process to a Xilinx Native Generic Database (NGD) file and Xilinx Project Navigator project (NPL) file. Individual Build stages, options and the corresponding default script files are described in the following sections. Be aware that these scripts are defaulted to standard optimization – any changes should be carefully applied in consultation with the Xilinx Development System Reference Guide. The location in the design and the error or warning is logged in a report file, accessed by clicking on the appropriate Report icon ( ).įor advanced users who want more control over the options passed to the Xilinx tools, each stage in the Build process is linked to a script file located in the \System folder of the installation. Errors or design rules that are not allowed for your target architecture or in the design will be picked up at each stage of the Build process. Constituent stages of the Build process.Ĭlick the Options icon ( ) adjacent to each stage to configure that feature. By clicking on the down arrow, a list of individual steps used to complete the Build process can be found (Figure 1).įigure 1.
The Build process allows interface with Xilinx tools and produces the bitstream (BIT) file to download into your FPGA. This is done by including a suitable device constraint in a project constraint file, which belongs to a current project configuration ( Project » Configuration Manager).
Have the appropriate Xilinx vendor tools installed – either the full tool suite or the freely downloadable version available from the Xilinx website – and.To enable and display the Process Flow when the target device is a Xilinx FPGA you must: The place and route tools are all accessed and configured from the Build stage of the Process Flow associated to the target physical device in the Devices view.